1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a dual-die integrated circuit package which can be used to pack two semiconductor dies in the same package unit.
2. Description of Related Art
A dual-die integrated circuit package is a type of integrated circuit package that contains two semiconductor dies therein so that a single unit of integrated circuit package can offer a doubled level of functionality or capacity than a single-die integrated circuit package. However, needless to say, a dual-die integrated circuit package would be greater in size than a single-die integrated circuit package. To allow a dual-die integrated circuit package to be nevertheless small in size, various packaging methods have been proposed. Some of these methods are briefly depicted in the following with reference to FIGS. 6, 7, 8, 9, and 10A-10C.
FIG. 6 is a schematic sectional diagram of a first conventional dual-die integrated circuit package structure. As shown, the package structure 1 includes a leadframe having a die pad 10 for mounting two semiconductor dies including a first semiconductor die 12a and a second semiconductor die 12b. The first semiconductor die 12a is adhered to the top side of the die pad 10 through silver paste 11a, while the second semiconductor die 12b is adhered to the bottom side of the same through silver paste 11b. Further, the first semiconductor die 12a is electrically coupled to the corresponding inner leads 140 of the leads 14 via a first set of bonding wires 13a; and in a similar manner, the second semiconductor die 12b is electrically coupled to the corresponding inner leads 140 of the leads 14 via a second set of bonding wires 13b. Finally, an encapsulant 15 is formed to encapsulate the first and second semiconductor dies 12a, 12b, the die pad 10, the first and second sets of bonding wires 13a, 13b, and the inner leads 140 of the leadframe 14, while exposing the outer leads 141 of the leads 14 to the outside for external connections.
During manufacture of the package structure 1, it is required to perform the die-bonding process in two steps: a first step for mounting the first semiconductor die 12a on the upper side of the die pad 10, and then a second step, which is performed by turning the entire die pad 10 upside down, for mounting the second semiconductor die 12b on the bottom side of the die pad 10. As shown in FIG. 7, in this second step, the die pad 10 is positioned on a fixture 16, and then a presser 17 is used to press down against the second semiconductor die 12b after it is mounted on the bottom side of the die pad 10.
One drawback to the forgoing die-bonding process, however, is that since the functional surface of the first semiconductor die 12a, namely, the surface of the semiconductor die 12a on which electronic components and electric circuits are formed, comes in contact with the surface of the fixture 16, the pressing down of the presser 17 would easily cause damage to the functional surface of the first semiconductor die 12a. Moreover, during the mounting of the first semiconductor die 12a onto the die pad 10, since the die pad 10 has its bottom side come in contact with the platform of the die-bonding machine, it would easily cause contamination to the bottom side of the die pad 10 where the second semiconductor die 12b is to be mounted; and consequently, delamination would occur at the interface between the second semiconductor die 12b and the die pad 10. Still moreover, since the die-bonding process requires the die pad 10 to be turned upside down for the mounting of the second semiconductor die 12b, it would be highly difficult to align the second semiconductor die 12b precisely to the first semiconductor die 12a; if misaligned, it would degrade the quality of the resulting integrated circuit package.
Further, the subsequent wire-bonding process is also required to be performed in two steps: a first step for bonding the first set of bonding wires 13a to the first semiconductor die 12a while positioning the first semiconductor die 12a on the top side of the die pad 10, and then a second step, which is performed by turning the entire die pad 10 upside down, for bonding the second set of bonding wires 13b to the second semiconductor die 12b. 
One drawback to the foregoing wire-bonding process, however, is that when the die pad 10 is turned upside down subsequent to the wire bonding of the first set of bonding wires 13a, it would easily cause the first set of bonding wires 13a to come in contact with the fixture 16, thus making the first set of bonding wires 13a easily deformed or damaged. Moreover, since the wire bonding of the first set of bonding wires 13a is carried out under a high-temperature condition and during which the bottom side 140b of the inner leads 140 comes in contact with the heating plate of the wire bonding machine, it would tend to cause the bottom side 140b of the inner leads 140 to be oxidized and contaminated, which would considerably affect the bonding quality between the second set of bonding wires 13b and the bottom side 140b of the inner leads 140.
One solution to the foregoing drawbacks is the TAB (Tape Automated Bonding) method. FIG. 8 shows a dual-die integrated circuit package which utilizes the TAB method to electrically connect the semiconductor die and the leads. As shown, the integrated circuit package 2 is used to pack two semiconductor dies including a first semiconductor die 24a and a second semiconductor die 24b, and includes a leadframe consisting of a die pad 20 and a plurality of leads 21, each having an inner lead 210 and an outer lead 211. The integrated circuit package 2 also includes a plurality of TAB leads 22a, 22b for electrical connections of the semi-conductor dies 24a and the corresponding leads 21. The top TAB leads 22a have a middle section attached by an insulative tape 23a on the top side of the die pad 20, a first end electrically connected to the top surface 210a of the inner lead 210, and a second end electrically connected to the bonding pads (not shown) on the first semiconductor die 24a; and in a similar manner, the bottom TAB leads 22b have a middle section attached by an insulative tape 23b on the bottom side of the die pad 20, a first end electrically connected to the bottom surface 210b of the inner lead 210, and a second end electrically connected to the bonding pads (not shown) on the second semiconductor die 24b. This arrangement allows the two semiconductor dies 24a, 24b to be respectively electrically coupled via the TAB leads 22a, 22b to the leads 21.
The TAB technique can help eliminate the drawbacks of the dual-die integrated circuit package structure of FIG. 6. However, since the use of the TAB technique requires the bonding pads on the semiconductor dies to be made from gold, it would significantly increase the manufacture cost. Moreover, it must be implemented by the use of a special machine called a gang bonding machine, which would further increase the manufacture cost since this type of machine is quite expensive as compared to conventional wire bonding machines. Further, the TAB technique requires complex processing steps so that the resulted integrated circuit packages are less reliable than the ones having conventional bonding wires.
As a solution to the drawbacks of the foregoing two dual-die integrated circuit package structures, U.S. Pat. No. 5,545,922 proposes a dual-die integrated circuit package having offset bonding wires, as illustrated in FIG. 9. As shown, the integrated circuit package 3 is used to pack two semiconductor dies including a first semiconductor die 32a and a second semiconductor die 32b. The first semiconductor die 32a is adhered by silver paste 31a on the top side of the die pad 30, while the second semiconductor die 32b is adhered by silver paste 31b on the bottom side of the same. Further, the first semiconductor die 32a is electrically coupled via a first set of bonding wires 33a to the front sides 340b of the inner leads 340 of the leads 34, while the second semi-conductor die 32b is electrically coupled via a second set of bonding wires 33b to bottom sides 340b of the inner leads 340 of the leads 34. Finally, an encapsulant 35 is formed to encapsulate the two semiconductor dies 32a, 32b, the two sets of bonding wires 33a, 33b, and the inner leads 340 of the leads 34, while exposing the outer leads 341 of the leads 34.
The die-bonding process for the foregoing dual-die integrated circuit package includes two steps: a first step to adhere the first semiconductor die 32a onto the top side of the die pad 30; and then, with the entire die pad 30 being turned upside down and fixed on a fixture 36 as shown in FIG. 10A, a second step to adhere the second semiconductor die 32b to the bottom side of the die pad 30. During the second step, the first semiconductor die 32a is accommodated within a void portion 36a in the fixture 36, and a presser 37 is used to press down against the die pad 30 for the purpose of fixing the die pad 30 firmly in position. After this, the subsequent wire-bonding process also includes two steps, as respectively depicted in FIGS. 10B and 10C. As shown in FIG. 10B, in the first step, the die pad 30 is turned upside down to have the first semiconductor die 32a positioned above the second semiconductor die 32b, and the inner leads 340 are fixed by the fixture 36 and the presser 37 so as to fix the entire leadframe firmly in position; and then, the first set of bonding wires 33a are bonded between the first semi-conductor die 32a and the top surface 340a of the inner leads 340. Next, as shown in FIG. 10C, the semi-finished package structure is remounted on another fixture 38 having a void portion 38a for accommodating the first semiconductor die 32a and the first set of bonding wires 33a. The die pad 30 is fixed in position by clamping the inner leads 340 of the leads 34 with the presser 37 and the fixture 38. With this setup, the second step of the wire-bonding process is performed to bond the second set of bonding wires 33b between the second semiconductor die 32b and the bottom surface 340b of the inner leads 340 of the leads 34. It can be seen from FIG. 10C that the ends of the second set of bonding wires 33b coupled to the inner leads 340 are more outwardly located with respect to the ends of the first set of bonding wires 33a coupled to the inner leads 340 (the so-called offset bonding wires).
The foregoing dual-die integrated circuit package can help prevent the upside-down turned first semiconductor die 32a and the first set of bonding wires 33a from coming in contact with any surface of the fixture that would otherwise cause damage to the functional surface of the first semiconductor die 32a and the bonding wires 33a. However, it still has the following drawbacks.
First, after the die-bonding process for the first semiconductor die 32a is completed, the subsequent curing process would cause the bottom side of the die pad 30 to be contaminated, making the die bonding of the second semiconductor die 32b to the bottom side of the die pad 30 still have delamination problems.
Second, delamination would arise at the interface between the first semiconductor die 32a and the die pad 30. This is because during the die-bonding process for the second semiconductor die 32b, there is no support beneath the die pad 30 since the underneath of the die pad 30 is the void portion 36a. 
Third, since the interface between each semiconductor die 32a or 32b and the die pad 30 is quite large in area, the CTE (Coefficient of Thermal Expansion) difference between them would cause delamination to the interface during the curing process.
Fourth, during the wire-bonding process for the first semiconductor die 32a, since the bottom side 340b of the inner leads 340 would come into direct contact with the fixture 38 which is heated up to 220xc2x0 C., it would easily cause the bottom side 340b of the inner leads 340 to be oxidized and contaminated, which would degrade the bonding of the second set of bonding wires 33b. 
Fifth, the die-bonding process requires the use of various kinds of fixtures, which would make equipment management quite laborious and time-consuming, and thus cost-ineffective to implement.
Sixth, during the die-bonding process, it would not be easy to align the two semiconductor dies 3a, 3b with respect to each other, which would degrade the quality of the resulting integrated circuit package. This is because the die-bonding process for the second semiconductor die 3b is carried out after the first semiconductor die 32a has already been mounted in position, making it difficult to provide a precise alignment.
Seventh, the wire-bonding process requires the use of various kinds of fixtures, which would make equipment management quite laborious and time-consuming, and thus cost-ineffective to implement.
U.S. Pat. No. 5,677,567 to Ma et al. discloses a multiple-die semiconductor package with a leadframe having a plurality of lead fingers and including at least one lead of non-uniform length and configuration that can attach to the semiconductor dies. For example, as shown in FIG. 9, a multiple die assembly 900 contains four dies 806, 808, 812, and 814, and leadframes 901 and 903. Each leadframe 901, 903 has leads extending between the dies from more than one side, e.g., leadframe 901 includes leads 902 extending from laterally opposite directions between dies 806 and 808. Additionally, paddles 906 and 908 are positioned between dies 806 and 808, and dies 812 and 814, respectively. Each paddle is arranged on the same lateral plane as the lead fingers, e.g., lead fingers 902 extend from either side between dies 806 and 808, and paddle 906 is positioned parallel to the lead fingers 902 on the same lateral plane. Dies 806, 808, 812 and 814 are supported primarily by leads 902 and 904, respectively, and each die can have its active surface 820, 826, 830, and 836 adhered to paddles 906 and 908. Because each leadframe 901, 903 is mounted with two dies respectively on opposite sides thereof, it is necessary to turn the leadframe upside-down for depositing a latter-mounted die thereon, which requires additional steps in the manufacturing process.
In conclusion, the foregoing conventional packaging methods for dual-die integrated circuit packages are still unsatisfactory to use. There exists a new packaging method that can help eliminate the above-mentioned drawbacks of the prior art.
It is therefore an objective of this invention to provide a dual-die integrated circuit package, which can be manufactured using conventional equipment and processes.
It is another objective of this invention to provide a dual-die integrated circuit package structure, which allows the interface between each semiconductor die and the die pad to be small in area so as to reduce the occurrence of delamination.
It is still another objective of this invention to provide a dual-die integrated circuit package, which can be manufactured without causing contamination to both sides of the die pad and the functional surface of each semiconductor die.
It is yet another objective of this invention to provide a dual-die integrated circuit package, which can be manufactured in a more cost-effective manner than the prior art.
It is still yet another objective of this invention to provide a dual-die integrated circuit package, which allows the two semiconductor dies on the die pad to be easily aligned to each other.
In accordance with the foregoing and other objectives, the invention proposes a new dual-die integrated circuit package. The dual-die integrated circuit package of the invention includes the following constituent parts: (a) a first leadframe having a die pad and a plurality of leads disposed along one side of the die pad; (b) a second leadframe having a die pad and a plurality of leads disposed along one side of the die pad, wherein the die pads of the first and second leadframes are laterally positioned between the leads of the first leadframe and the leads of the second leadframe, and the die pad of the second leadframe is arranged in a staggered and laterally offset manner with respect to the die pad of the first leadframe; (c) a first semiconductor die having an active surface formed with a plurality of bonding pads thereon, and an inactive surface opposed to the active surface, the inactive surface having a portion thereof being adhered to the die pad of the first leadframe and a non-adhered portion being positioned away from the leads of the first leadframe; (d) a second semiconductor die having an active surface formed with a plurality of bonding pads thereon, and an inactive surface, the inactive surface having a portion thereof being adhered to the die pad of the second leadframe, and a non-adhered portion being positioned away from the leads of the second leadframe, wherein the non-adhered portion of the second semiconductor die is separated from the die pad of the first leadframe, and the non-adhered portion of the first semiconductor die is separated from the bottom surface of the die pad of the second leadframe, and wherein the die pads of first and second leadframes are each positioned in elevation between the first semiconductor die and the second semiconductor die; (e) a first set of electrical connection means for electrically coupling the bonding pads on the active surface of the first semiconductor die to the corresponding leads of the first leadframe; (f) a second set of electrical connection means for electrically coupling the bonding pads on the active surface of the second semiconductor die to the corresponding leads of the second leadframe; and (g) an encapsulant for encapsulating the first and second semiconductor dies, the die pads of the first and second leadframes, and a part of the leads of the first and second leadframes.
The foregoing dual-die integrated circuit package is characterized in the use of two leadframes, each having a die pad and a plurality of leads each defined into an inner lead and an outer lead. The two semiconductor dies are mounted on the respective die pads of the two leadframes, with the inactive bottom surface of each semiconductor die facing the inactive bottom surface of the other, allowing a clearance to be formed between the bottom surface of the second semiconductor die and the die pad of the first leadframe, and a clearance to be formed between the bottom surface of the first semiconductor die and the die pad of the second leadframe. Moreover, the die pad of the leadframe used in the invention is smaller in area than the semiconductor die so as to allow the die pad of the leadframe to be adhered to merely a part of the bottom surface of the semiconductor die. By this arrangement, delamination between the semiconductor die and the die pad of the leadframe can be eliminated due to the reduced interface between the semiconductor die and the die pad. To further decrease the interface between the semiconductor die and the die pad, the die pad can be formed with at least one opening. Therefore, this dual-die integrated circuit package can help prevent delamination and also allows the manufacture to be more cost-effective to implement than the prior art. The die pad may be vertically positioned downset relative to a second plane from a first plane where the leads are positioned so as to allow the leads of the first and second leadframes to be horizontally aligned, after the encapsulant is formed. This arrangement also permits that in the dual-die integrated circuit package of the invention, the first semiconductor die is held in proximity to the second semiconductor die as close as possible, and thereby makes the resulted integrated circuit package low in profile. In the manufacture process of the dual-die integrated circuit package of the invention, the die bond process for the first semiconductor die is the same as that for the second semiconductor die, thereby the die-bonding of the first semiconductor die can be simultaneously preformed with the die-bonding of the second semiconductor die with the same die bonded equipments and processes. As a result, the dual-die integrated circuit package of the invention is more cost-effective and time-efficient to manufacture than the prior art. Moreover, as the die bond process and the wire bond process need not to turn over the combined structure of the leadframe and the semiconductor die so that there exists no contamination concern which would otherwise cause delamination and/or degrade the wire bond quality.